DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 376

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.3
TDPWDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1
(cycle measurement mode), TDPWDMN is available as a pulse width lower limit register.
In cycle measurement mode, TDPWDMN can be used to set the lower limit value of measurement
pulse width. When the second edge (the second edge of this period) of the measurement period is
detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and
TDPWDMN are compared. If the TDPICR value is less than the TDPWDMN value, the
TWDMNUDF flag in TDPCSR is set to 1. TDPWDMN must always be accessed in 16-bit units
and cannot be accessed in 8-bit units. TDPWDMN is initialized to H'0000.
12.3.4
TDPPDMX is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1
(cycle measurement mode), TDPPDMX is available as a cycle upper limit register.
In cycle measurement mode, TDPPDMX can be used to set the upper limit value of measurement
period. When the third edge (the first edge of the next period) of the measurement period is
detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPPDMX
are compared. If the TDPICR value is greater than the TDPPDMX value, the TPDMXOVF flag in
TDPCSR is set to 1. TDPPDMX must always be accessed in 16-bit units and cannot be accessed
in 8-bit units. TDPPDMX is initialized to H'FFFF.
12.3.5
TDPPDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1
(cycle measurement mode), TDPPDMN is available as a cycle lower limit register.
In cycle measurement mode, TDPPDMN can be used to set the lower limit value of measurement
period. When the third edge (the first edge of the next period) of the measurement period is
detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPPDMN
are compared. If the TDPICR value is less than the TDPPDMN value, the TPDMNUDF flag in
TDPCSR is set to 1. TDPPDMN must always be accessed in 16-bit units and cannot be accessed
in 8-bit units. TDPPDMN is initialized to H'0000.
Rev. 2.00 Sep. 28, 2009 Page 334 of 994
REJ09B0452-0200
TDP Pulse Width Lower Limit Register (TDPWDMN)
TDP Cycle Upper Limit Register (TDPPDMX)
TDP Cycle Lower Limit Register (TDPPDMN)