DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 481

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)
No
No
No
Read ORER and FER flags in SSR
Read ORER and FER flags in SSR
Read receive data in RDR
Read receive data in RDR
Set MPIE bit in SCR to 1
Read RDRF flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
All data received?
FER ∨ ORER = 1
This station’s ID?
FER ∨ ORER = 1
Start reception
End reception
Initialization
RDRF = 1
RDRF = 1
Yes
Yes
Yes
Yes
No
No
Yes
No
Error processing
Yes
(Continued on next page)
[3]
[6]
[1]
[2]
[4]
[5]
[1] SCI initialization:
[2] ID reception cycle:
[3] SCI status check, ID reception and
[4] SCI status check and data reception:
[5] Receive error processing and break
Note:
[Legend]
∨: Logical add (OR)
The RxD pin is automatically
designated as the receive data input
pin.
Set the MPIE bit in SCR to 1.
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set
the MPIE bit to 1 again, and clear the
RDRF flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the ORER and FER flags are all
cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD
pin value.
Do not write to SMR, SCR, BRR,
and SDCR from the start to the
end of reception except the
process of [6].
Rev. 2.00 Sep. 28, 2009 Page 439 of 994
REJ09B0452-0200