DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 18

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00 Sep. 28, 2009 Page xvi of xl
REJ09B0452-0200
Item
20.3.11 Bidirectional
Data Registers 0 to 15
(TWR0 to TWR15)
20.3.12 Status
Registers 1 to 4 (STR1
to STR4)
• STR4
21.4.5 FSI Memory
Cycle (LPC-SPI
Command Transfer)
Figure 21.13 FSI
Command Read
(Example)
21.5 Reset Conditions
Table 21.8 Range of
Initialization of FSI in
Each Mode
Page
638
644
716
723, 724 Table amended
Revision (See Manual for Details)
Description amended
When the host and slave begin a write, after the respective
registers of TWR0 have been written to, arbitration for
simultaneous access is performed by checking the status flags
whether or not those writes were valid.
When the host has access rights, TWR0MW is selected in
TWR0 and the state of TWR0MW is returned when the host
reads TWR0SW. Attempts by the slave to write to TWR0SW
are invalid.
When the slave has access rights, TWR0SW is selected in
TWR0 and the state of TWR0SW is returned when the slave
reads TWR0MW. Attempts by the host to write to TWR0MW
are invalid.
For the registers selected from the host according to the I/O
address, see section 20.3.7, LPC Channel 3 Address Registers
H and L (LADR3H and LADR3L).
Table amended
Figure amended
Bit
0
Register Name
FSILSTR1
FSISTR
Bit Name Initial Value Slave Host Description
OBF4
Bits 7, 6, 4,
and 3
Bit 2
Bits 5, 1, and
0
Bits 6 and 5
0
FSIGPR2 to D
FSILSTR1
FSIGPRE
FSIGPR1
FSIGPRF
System
Reset
Initialized
Initialized
Initialized
Initialized
R/(W)* R
R/W
LPC Reset
Initialized
Initialized
Retained
Retained
Output Buffer Full
0: [Clearing conditions]
1: [Setting condition]
When the slave writes to ODR4
When the host reads ODR4 in I/O read cycle
When the slave writes 0 to the OBF4 bit
LPC internal flags
EC CPU write
LPC
Shutdown
Retained
Retained
Retained
Retained
LPC Abort
Retained
Retained
Retained
Retained
FSI Reset
Retained
Initialized
Retained
Initialized