DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 23

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
24.12 Standard Serial
Communication Interface
Specifications for Boot
Mode
Figure 24.18 Boot
Program States
(3) Inquiry and Selection
States
(f) Operating Clock
Frequency Inquiry
(8) Programming/Erasing
State
3. Programming/Erasing
State Information
(c) 128-Byte
Programming
(f) Memory Read
Page
803
811
823
826
Revision (See Manual for Details)
Figure amended
Description amended
• Minimum value of operating clock frequency (two bytes): The
• Maximum value (two bytes): Maximum value among the
Description amended
• ERROR: (one byte): Error code
Description amended
• Area (one byte)
There are as many pairs of minimum and maximum values
as there are operating clock frequencies.
minimum value of the
divided clock frequencies.
H'11: Checksum Error
H'2A: Address Error
H'53: Programming error
H'00: User boot MAT
H'01: User MAT
The minimum and maximum values of the operating clock
frequency represent the values in MHz, valid to the
hundredths place of MHz, and multiplied by 100. (e.g. when
the value is 17.00 MHz, it will be 2000, which is H'07D0.)
The address is not within the specified MAT range.
An address error occurs when the area setting is
incorrect.
A programming error has occurred and programming
cannot be continued.
Operations for erasing
Rev. 2.00 Sep. 28, 2009 Page xxi of xl
Programming/
divided clock frequency.
erasing wait
user boot MATs
user MATs and
Programming
REJ09B0452-0200