DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 687

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.3.13 SERIRQ Control Register 0 (SIRQCR0)
SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
Bit
7
6
5
Bit Name Initial Value Slave Host Description
Q/C
SELREQ 0
IEDIR2
0
0
R
R/W
R/W
R/W
Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.
Start Frame Initiation Request Select
Selects the condition of a start frame initiation
request when a host interrupt request is cleared in
quiet mode.
0: Start frame initiation is requested when all
1: Start frame initiation is requested when one or
Interrupt Enable Direct Mode 2
Selects whether an SERIRQ interrupt generation of
LPC channel 2 is affected only by a host interrupt
enable bit or by an OBF flag in addition to the enable
bit.
0: A host interrupt is generated when both the enable
1: A host interrupt is generated when the enable bit
interrupt requests are cleared
more interrupt requests are cleared
bit and the corresponding OBF flag are set
is set
LPC hardware reset, LPC software reset
Specification by SERIRQ transfer cycle stop
frame
Rev. 2.00 Sep. 28, 2009 Page 645 of 994
REJ09B0452-0200

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