DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 750

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 and the FSIDMYE bit in
FSILSTR1 are cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in SLCR are set to
1, the SPI flash memory address and write data are stored in FSIAR and FSIWDR, respectively.
Then, the SPI flash memory address, the write data, and the Byte/Page-Program instruction which
is stored in FSIPPINS in advance are transferred to FSITDR. After SYNC (long wait) has been
returned, the TE bit in FSICR2 is set, starting the Byte/Page-Program instruction execution. When
the transmission has been completed, SYNC (Ready) and TAR are returned to the host. To
execute the Byte-Program instruction, byte transfer access in LPC memory write cycle or FW
memory write cycle should be performed. Figure 21.4 shows an example of data transfer to
FSITDR. Figure 21.5 shows the Page-Program instruction execution timing.
Rev. 2.00 Sep. 28, 2009 Page 708 of 994
REJ09B0452-0200
FSIWDR[31:0]
FSIAR[23:0]
Byte/Page-Program Instruction
H'67_45_23_01
FSIPPINS[7:0]
H'06_4A_70
H'02
Figure 21.4 Data Transfer to FSITDR (Example)
FSIWDR[31:24]
FSIWDR[23:16]
FSIWDR[15:8]
FSIWDR[7:0]
FSIAR[7:0]
FSIAR[15:8]
FSIAR[23:16]
FSISFR
H'4A
H'67
H'45
H'23
H'01
H'70
H'06
H'02
FSITDR7
FSITDR6
FSITDR0
FSIDO