DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 753

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4)
If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI
flash memory address is stored in FSIAR. Then, the SPI flash memory address and the instruction
which is stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has
been returned, the RE bit in FSICR2 is set, and Read instruction execution starts. The read data is
then received and stored in FSIRDR. When the reception has been completed, SYNC (Ready),
read data, and TAR are returned to the host. Figure 21.8 shows an example of data transfer to
FSIRDR. Figure 21.9 shows the Read instruction execution timing.
LCLK
LFRAME
LAD[3:0]
φ
FSIAR[23:0]
FSIWDR[31:0]
FSICR2 TE bit
FSITDR7 to
FSITDR0
FSISTR OBF bit
FSISS
FSICK (CPOS = CPHS =0)
FSIDO
Read Instructions
CT
Figure 21.7 AAI-Program Instruction Execution Timing
ADDR
DATA TAR
(Second and Following Bytes)
H'23-AF
WAIT
Rev. 2.00 Sep. 28, 2009 Page 711 of 994
H'AF->23
H'06-4A-70
H'23
REJ09B0452-0200
SY TAR