DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 582

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 I
18.3.4
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Rev. 2.00 Sep. 28, 2009 Page 540 of 994
REJ09B0452-0200
Bit
7
6
5
4
3
MLS
Bit Name
WAIT
CKS2
CKS1
CKS0
I
2
C Bus Mode Register (ICMR)
2
C Bus Interface (IIC)
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
This bit is valid only in master mode with the I
format.
0: Data and the acknowledge bit are transferred
1: After the fall of the clock for the final data bit (8
For details, see section 18.4.7, IRIC Setting Timing and
SCL Control.
Transfer Clock Select 2 to 0
These bits are used only in master mode.
These bits select the required transfer rate, together
with the IICX2 (IIC_2), IICX1 (IIC_1), and IICX0 (IIC_0)
bits in STCR. See table 18.4.
consecutively with no wait inserted.
clock), the IRIC flag is set to 1 in ICCR, and a wait
state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and
the acknowledge bit is transferred.
2
C bus format is used.
2
C bus
th

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