DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 36

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4 Operation ........................................................................................................................... 514
17.5 Interrupt Sources................................................................................................................ 528
17.6 Usage Note......................................................................................................................... 528
Section 18 I
18.1 Features.............................................................................................................................. 529
18.2 Input/Output Pins............................................................................................................... 533
18.3 Register Descriptions ......................................................................................................... 534
18.4 Operation ........................................................................................................................... 560
Rev. 2.00 Sep. 28, 2009 Page xxxiv of xl
REJ09B0452-0200
17.3.7 Interrupt Identification Register (FIIR)................................................................. 500
17.3.8 FIFO Control Register (FFCR)............................................................................. 502
17.3.9 Line Control Register (FLCR) .............................................................................. 503
17.3.10 Modem Control Register (FMCR)........................................................................ 504
17.3.11 Line Status Register (FLSR)................................................................................. 506
17.3.12 Modem Status Register (FMSR)........................................................................... 510
17.3.13 Scratch Pad Register (FSCR)................................................................................ 511
17.3.14 SCIF Control Register (SCIFCR) ......................................................................... 512
17.4.1 Baud Rate ............................................................................................................. 514
17.4.2 Operation in Asynchronous Communication........................................................ 515
17.4.3 Initialization of the SCIF ...................................................................................... 516
17.4.4 Data Transmission/Reception with Flow Control................................................. 519
17.4.5 Data Transmission/Reception Through the LPC Interface ................................... 525
17.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 528
17.6.2 FLCR Access During Serial Transmission and Reception ................................... 528
18.3.1 I
18.3.2 Slave Address Register (SAR).............................................................................. 537
18.3.3 Second Slave Address Register (SARX) .............................................................. 538
18.3.4 I
18.3.5 I
18.3.6 I
18.3.7 I
18.3.8 I
18.4.1 I
18.4.2 Initialization.......................................................................................................... 562
18.4.3 Master Transmit Operation ................................................................................... 562
18.4.4 Master Receive Operation .................................................................................... 567
18.4.5 Slave Receive Operation....................................................................................... 570
18.4.6 Slave Transmit Operation ..................................................................................... 574
18.4.7 IRIC Setting Timing and SCL Control ................................................................. 577
18.4.8 Noise Canceler...................................................................................................... 579
2
C Bus Interface (IIC).......................................................................529
2
2
2
2
2
2
2
C Bus Data Register (ICDR) .............................................................................. 536
C Bus Mode Register (ICMR)............................................................................ 540
C Bus Control Register (ICCR).......................................................................... 543
C Bus Status Register (ICSR)............................................................................. 551
C Bus Control Initialization Register (ICRES)................................................... 555
C Bus Extended Control Register (ICXR).......................................................... 556
C Bus Data Format ............................................................................................. 560