DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 147

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• WER
5.4
5.4.1
The interrupt sources of external interrupts are NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15
to WUE8. These interrupts can be used to restore this LSI from software standby mode.
(1)
The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or falling
edge on the NMI pin.
(2)
Interrupts IRQ15 to IRQ0 are requested by an input signal at pins IRQ15 to IRQ0 or pins
ExIRQ15 to ExIRQ6. Interrupts IRQ15 to IRQ0 have the following features:
• The interrupt exception handling for interrupt requests IRQ15 to IRQ0 can be started at an
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to
Bit
7
6 to 0 ⎯
independent vector address.
edge, rising edge, or both edges, at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ6.
0 by software.
NMI Interrupt
IRQ15 to IRQ0 Interrupts:
Bit Name
WUEE
Interrupt Sources
External Interrupt Sources
Initial Value
0
All 0
R/W
R/W
R/W
Description
WUE Enable
The WUE interrupt request is enabled when this bit|
is 1.
0: Wake-up input interrupt request is disabled
1: Wake-up input interrupt request is enabled
Reserved
The initial values should not be changed.
Rev. 2.00 Sep. 28, 2009 Page 105 of 994
REJ09B0452-0200