DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 37

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.5 Interrupt Sources................................................................................................................ 581
18.6 Usage Notes ....................................................................................................................... 582
Section 19 Keyboard Buffer Control Unit (PS2).................................................587
19.1 Features.............................................................................................................................. 587
19.2 Input/Output Pins ............................................................................................................... 589
19.3 Register Descriptions ......................................................................................................... 590
19.4 Operation ........................................................................................................................... 599
19.5 Usage Notes ....................................................................................................................... 613
Section 20 LPC Interface (LPC) ..........................................................................615
20.1 Features.............................................................................................................................. 615
20.2 Input/Output Pins ............................................................................................................... 617
20.3 Register Descriptions ......................................................................................................... 618
18.4.9 Initialization of Internal State ............................................................................... 579
18.6.1 Module Stop Mode Setting ................................................................................... 585
19.3.1 Keyboard Control Register 1 (KBCR1)................................................................ 591
19.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 593
19.3.3 Keyboard Control Register H (KBCRH) .............................................................. 594
19.3.4 Keyboard Control Register L (KBCRL) ............................................................... 596
19.3.5 Keyboard Data Buffer Register (KBBR) .............................................................. 598
19.3.6 Keyboard Buffer Transmit Data Register (KBTR) ............................................... 598
19.4.1 Receive Operation................................................................................................. 599
19.4.2 Transmit Operation ............................................................................................... 601
19.4.3 Receive Abort ....................................................................................................... 602
19.4.4 KCLKI and KDI Read Timing.............................................................................. 605
19.4.5 KCLKO and KDO Write Timing.......................................................................... 605
19.4.6 KBF Setting Timing and KCLK Control .............................................................. 606
19.4.7 Receive Timing..................................................................................................... 607
19.4.8 Operation during Data Reception ......................................................................... 607
19.4.9 KCLK Fall Interrupt Operation............................................................................. 608
19.4.10 First KCLK Falling Interrupt ................................................................................ 609
19.5.1 KBIOE Setting and KCLK Falling Edge Detection.............................................. 613
19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 614
19.5.3 Module Stop Mode Setting ................................................................................... 614
19.5.4 Medium-Speed Mode............................................................................................ 614
19.5.5 Transmit Completion Flag (KBTE) ...................................................................... 614
20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 620
20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 626
20.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 629
Rev. 2.00 Sep. 28, 2009 Page xxxv of xl
REJ09B0452-0200