DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 752

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 is set to 1 and the
FSIDMYE bit in FSILSTR1 is cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in
SLCR are set to 1, the flash memory address and write data are stored in FSIAR and FSIWDR,
respectively. Then, the flash memory address, write data, and the AAI-Program instruction which
is stored in FSI hardware in advance are transferred to FSITDR. After SYNC (long wait) has been
returned, the transmit enable signal TE is set, and AAI-Program instruction execution starts. In the
first byte, the instruction, address, and data in this order are transmitted to the SPI flash memory.
In the second and the following bytes, an instruction and data in this order are transmitted to the
SPI flash memory. When the transmission has been completed, SYNC (Ready) and TAR are
returned to the host. To execute the AAI-Program instruction, byte transfer access in LPC memory
write cycle or FW memory write cycle should be performed. To return to the AAI-Program
instruction (first byte), clear the AAIE bit once or perform initialization of the FSI internal
sequencer in SRES of FSICR1. After the Read instruction or the LPC-SPI command is transferred
during the AAI-Program instruction execution, the FSI internal sequencer is initialized to return to
the AAI-Program Instruction (first byte). Figures 21.6 and 21.7 show AAI-Program execution
timings.
Rev. 2.00 Sep. 28, 2009 Page 710 of 994
REJ09B0452-0200
LCLK
LFRAME
LAD[3:0]
φ
FSIAR[23:0]
FSIWDR[31:0]
FSICR2 TE bit
FSITDR7 to
FSITDR0
FSISTR OBF bit
FSISS
FSICK (CPOS = CPHS = 0)
FSIDO
AAI-Program Instruction
Figure 21.6 AAI-Program Instruction Execution Timing (First Byte)
ST CT
ADDR
DATA TAR
H'01-70-4A-06-AF
WAIT
H'AF->06->4A->70->01
H'01
H'06-4A-70
SY TAR