DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 797

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1)
This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The
on-chip program to be downloaded is selected by the programming/erasing interface registers. The
start address of the on-chip RAM where an on-chip program is downloaded is specified by the
flash transfer destination address register (FTDAR).
(2)
The on-chip program is automatically downloaded by setting the flash key code register (FKEY)
and the SCO bit in the flash code control/status register (FCCS). The memory MAT is replaced
with the embedded program storage area during download. Since the memory MAT cannot be
read during programming/erasing, the procedure program must be executed in a space other than
the flash memory (for example, on-chip RAM). Since the download result is returned to the
programming/erasing interface parameter, whether download is normally executed or not can be
confirmed.
(3)
A pulse with the specified period must be applied when programming or erasing. The specified
pulse width is made by the method in which wait loop is configured by the CPU instruction.
Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The
operating frequency of the CPU is set by the programming/erasing interface parameter.
(4)
The start address of the programming destination and the program data are specified in 128-byte
units when programming. The block to be erased is specified with the erase block number in
erase-block units when erasing. Specifications of the start address of the programming destination,
program data, and erase block number are performed by the programming/erasing interface
parameters, and the on-chip program is initiated. The on-chip program is executed by using the
JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip
RAM. The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory. All
interrupts are disabled during programming/erasing.
Selection of On-Chip Program to be Downloaded
Download of On-Chip Program
Initialization of Programming/Erasing
Execution of Programming/Erasing
Rev. 2.00 Sep. 28, 2009 Page 755 of 994
REJ09B0452-0200