DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 578

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2
Section 18 I
C Bus Interface (IIC)
2
18.3.1
I
C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is internally divided into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among
these three registers are performed automatically in accordance with changes in the bus state, and
they affect the status of internal flags such as ICDRE and ICDRF.
2
In master transmit mode with the I
C bus format, writing transmit data to ICDR should be
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
In transmit mode (TRS = 1), transmit data can be written to ICDRT when the ICDRE flag is 1.
After the transmit data has been written to ICDRT, the ICDRE flag is cleared to 0. Then, when
ICDRS becomes empty on completion of the previous transmission, the data are automatically
transferred from ICDRT to ICDRS and the ICDRE flag is set to 1. As long as ICDRS contains
data to be transmitted or data being transmitted, data written to ICDRT are retained there.
In receive mode (TRS = 0), data is not transferred from ICDRT to ICDRS. Thus, do not write to
ICDRT when in this mode.
In receive mode (TRS = 0), data received in ICDRR can be read when the ICDRF flag is 1. After
the data has been read from ICDRR, the ICDRF flag is cleared to 0. Each time ICDRS contains
data on completion of one round of reception, the data is automatically transferred from ICDRS to
ICDRR and the ICDRF flag is set to 1. If ICDRR contains receive data that hasn’t been read out,
any further receive data is retained in ICDRS.
Since data are not transferred from ICDRS to ICDRR in transmit mode (TRS = 1), do not read
ICDRR in transmit mode (excluding the case where final receive data is read out in the
recommended operation flow of master receive mode).
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
Rev. 2.00 Sep. 28, 2009 Page 536 of 994
REJ09B0452-0200