DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 503

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.8.2
Table 15.14 shows the interrupt sources in smart card interface mode. A TEI interrupt request
cannot be used in this mode.
Table 15.14 SCI Interrupt Sources
In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a
TXI interrupt request. If an error occurs, the SCI automatically re-transmits the same data. During
re-transmission, the TEND flag remains 0. Therefore, the SCI automatically transmits the
specified number of bytes, including re-transmission in the case of error. However, the ERS flag
in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared
by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at
error occurrence.
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If an
error occurs, the RDRF flag is not set but the error flag is set. Therefore, an ERI interrupt request
is issued to the CPU instead; the error flag must be cleared.
Channel
1
2
Interrupts in Smart Card Interface Mode
Name
ERI1
RXI1
TXI1
ERI2
RXI2
TXI2
Interrupt Source
Receive error, error signal
detection
Receive data full
Transmit data empty
Receive error, error signal
detection
Receive data full
Transmit data empty
Interrupt Flag
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
TEND
Rev. 2.00 Sep. 28, 2009 Page 461 of 994
REJ09B0452-0200
Priority
High
Low

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