DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 17

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Item
20.1 Features
Figure 20.1 Block
Diagram of LPC
20.3 Register
Descriptions
Table 20.2 Register
Configuration
20.3.1 Host Interface
Control Registers 0 and
1 (HICR0 and HICR1)
• HICR1
20.3.2 Host Interface
Control Registers 2 and
3 (HICR2 and HICR3)
• HICR2
Page
616
619
625
627
Revision (See Manual for Details)
Figure amended
Table amended
Table amended
Table amended
Bit
0
Bit
3
Register Name
Bidirectional data register 0MW
Bidirectional data register 0SW
LSCIB
Bit Name
IBFIE3
Bit Name
Initial
Value
0
Initial
Value
0
Slave Host Description
R/W
Slave Host Description
R/W
TWR1 to
TWR15
TWR0MW
R/W
R/W
Abbreviation Slave Host
TWR0MW
TWR0SW
Rev. 2.00 Sep. 28, 2009 Page xv of xl
LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit
bit in HICR0.
IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRE = 0 in LADR3]
complete interrupt requests disabled
Input data register (IDR3) receive complete
interrupt requests enabled
[When TWRE = 1 in LADR3]
Input data register (IDR3) and TWR receive
complete interrupt requests enabled
. For details, refer to description on the LSCIE
R
W
IDR4
IDR3
IDR2
IDR1
R/W
W
R
Initial
Value Address
H'00
H'00
REJ09B0452-0200
H'FE20
H'FE20
Data Bus
Width
8
8

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