DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 764

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
21.4.6
The write operation to the SPI flash memory in the LPC/FW memory write cycles can be
classified into the following four operation modes, depending or the state of FLDCT and
FLWAIT.
Table 21.7 SPI Flash Memory Write Operation in LPC/FW Memory Write Cycles
Rev. 2.00 Sep. 28, 2009 Page 722 of 994
REJ09B0452-0200
Operation
Mode
Mode 1
Mode 2
Mode 3
Mode 4
SPI Flash Memory Write Operation Mode
FLDCT
0
0
1
1
FLWAIT
0
1
0
1
FSIWBUSY ← 1
FSIWBUSY ← 1
LFBUSY ← 1
LFBUSY ← 1
Selected Register
FSIWI ← 1
FSIWI ← 1
(Automatically
cleared)
(Automatically
cleared)
Operation
Control the write operation to the SPI
flash memory by the EC CPU. No wait
cycle is inserted to the LPC bus. Confirm
by FSIWBUSY whether or not a write
transfer has been completed.
Control the write operation to the SPI
flash memory by the EC CPU. Wait
cycles are inserted to the LPC bus.
Provision of wait cycles can be canceled
by clearing FSIWBUSY.
Control the write operation to the SPI
flash memory by the FSI. No wait cycle is
inserted to the LPC bus. Confirm by
LFBUSY whether or not a write transfer
has been completed.
Control the write operation to the SPI
flash memory by the FSI. Wait cycles are
inserted to the LPC bus. Provision of wait
cycles can be canceled by clearing
LFBUSY.

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