DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 351

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3.1
TCMCNT is a 16-bit readable/writable up-counter. The input clock is selected by the bits CKS2 to
CKS0 in TCMCR. When CKS2 to CKS0 are set to B'111, the external clock is selected. In this
case, the rising or falling edge is selected by CKSEG in TCMCR.
When TCMCNT overflows (counting changes the value from H'FFFF to H'0000), OVF in
TCMCSR is set to 1. When the CST bit in TCMCR is cleared in timer mode, TCMCR is
initialized to H'0000. In cycle measurement mode, TCMCNT is cleared by detection of the first
edge (the edge selected with the IEDG bit in TCMCR) of the measurement period (one period of
the input waveform forms one measurement period).
In timer mode, TCMCNT is always writable. TCMCNT cannot be modified in cycle measurement
mode. TCMCNT should always be accessed in 16-bit units and cannot be accessed in 8-bit units.
TCMCNT is initialized to H'0000.
11.3.2
TCMMLCM is a 16-bit readable/writable register. TCMMLCM is available as a compare match
register when the TCMMDS bit in TCMCR is cleared (operation is in timer mode). TCMMLCM
is available as a cycle upper limit register when the TCMMDS bit in TCMCR is set to 1 (operation
is in cycle measurement mode).
In timer mode, the value in TCMMLCM is constantly compared with that in TCMCNT, when the
values match, CMF in TCMCSR is set to 1. However, comparison is disabled in the second half of
a cycle of writing to TCMMLCM.
In cycle measurement mode, a value that sets an upper limit on the measurement period can be set
in TCMMLCM. When the second edge (first edge of the following cycle) of the measurement
period is detected, the value in TCMCNT is transferred to TCMICR. At this time, the values in
TCMICR and TCMMLCM are compared. The MAXOVF flag in TCMCSR is set to 1 if the value
in TCMICR is greater than that in TCMMLCM. TCMMLCM should always be accessed in 16-bit
units and cannot be accessed in 8-bit units. TCMMLCM is initialized to H'FFFF.
TCM Timer Counter (TCMCNT)
TCM Cycle Upper Limit Register (TCMMLCM)
Rev. 2.00 Sep. 28, 2009 Page 309 of 994
REJ09B0452-0200