DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 592

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 I
Table 18.6 Flags and Transfer States (Slave Mode)
MST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[Legend]
0:
1:
—:
0
1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
Rev. 2.00 Sep. 28, 2009 Page 550 of 994
REJ09B0452-0200
↓
↑
:
:
TRS
0
0
1↑/0
*
0
1↑/0
*
1
1
1
1
1
1
0
0
0
0
0
—
1
1
0-state retained
1-state retained
Previous state retained
Cleared to 0
Set to 1
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
BBSY ESTP STOP IRTR AASX AL
0
1↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0↓
2
C Bus Interface (IIC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1↑/0
*
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1↑
*
3
0
0
0
0
1↑
—
1↑/0
*
—
—
—
1↑/0
*
1↑/0
*
—
—
—
1↑/0
*
—
2
2
2
2
0
0↓
0
0
1↑
—
—
—
—
—
—
—
—
—
—
—
—
0
0
—
—
—
—
—
0↓
—
0↓
0
—
0↓
—
0↓
0
—
AAS
0
1↑
1↑
0
—
—
0↓
—
0↓
0
—
0↓
—
0↓
0
—
0
ADZ
0
0
0
1↑
0
0
0
0
1
0
0
—
0↓
—
0↓
0
—
ACKB ICDRF ICDRE State
0
0
0
0
0
1↑
0
0
0
0
0
—
—
—
—
—
—
—
—
1↑
1↑
1↑
—
—
—
1↑
0↓
1
0↓
1↑
—
0
1↑
1
1
1
—
1↑
0↓
1
0↓
1↑
—
—
—
—
—
0↓
Start condition detected
Transmission end (ACKE=1
and ACKB=1)
Transmission end with
ICDRE=0
ICDR write with the above
Transmission end with
ICDR write with the above
Automatic data transfer from
ICDRT to ICDRS with the
above state
Reception end with ICDRF=1
Automatic data transfer from
Stop condition detected
Idle state (flag clearing
required)
SAR match in first frame
(SARX≠SAR)
General call address match in
first frame (SARX≠H'00)
SAR match in first frame
(SAR≠SARX)
state
ICDRE=1
state
Reception end with ICDRF=0
ICDR read with the above
state
ICDR read with the above
state
ICDRS to ICDRR with the
above state