DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 496

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. In this
Figure 15.28 shows a sample flowchart for transmission. In transmission, the TEND and TDRE
flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request when TIE in SCR
is set. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission,
TEND remains 0. Therefore, the SCI automatically transmit the specified number of bytes,
including re-transmission in the case of error. However, the ERS flag is not automatically cleared;
the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt
request to be generated at error occurrence.
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR,
which is shown in figure 15.27.
Rev. 2.00 Sep. 28, 2009 Page 454 of 994
REJ09B0452-0200
TDRE
TEND
FER/ERS
case, one frame of data is determined to have been transmitted including re-transfer, and the
TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is
set to 1. Writing transmit data to TDR starts transmission of the next data.
I/O data
TXI
(TEND interrupt)
[Legend]
Ds:
D0 to D7: Data bits
Dp:
Ds
Figure 15.26 Data Re-transfer Operation in SCI Transmission Mode
Transfer from TDR to TSR
GM = 0
GM = 1
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Start bit
Parity bit
Figure 15.27 TEND Flag Set Timings during Transmission
nth transfer frame
Ds
DE:
etu:
D0
Error signal
Element Time Unit (time taken to transfer one bit)
D1
[1]
D2
[2]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
D3
Transfer from TDR to TSR
11.0 etu
12.5 etu
D4
Retransfer frame
D5
D6
D7
Dp
(DE)
[3]
[3]
Guard time
DE
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
transfer frame
(n + 1) th