DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 662

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.1
HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
• HICR0
Rev. 2.00 Sep. 28, 2009 Page 620 of 994
REJ09B0452-0200
Bit
7
6
5
Bit Name
LPC3E
LPC2E
LPC1E
Host Interface Control Registers 0 and 1 (HICR0 and HICR1)
Initial
Value
0
0
0
Slave Host Description
R/W
R/W
R/W
R/W
⎯
⎯
⎯
LPC Enables 3 to 1
Enable or disable the LPC interface function. When the
LPC interface is enabled (one of the three bits is set to
1), processing for data transfer between the slave (this
LSI) and the host is performed using pins LAD3 to
LAD0, LFRAME, LRESET, LCLK, SERIRQ, CLKRUN,
and LPCPD.
•
0: LPC channel 3 operation is disabled
1: LPC channel 3 operation is enabled
•
0: LPC channel 2 operation is disabled
1: LPC channel 2 operation is enabled
•
0: LPC channel 1 operation is disabled
1: LPC channel 1 operation is enabled
LPC3E
No address (LADR3) matches for IDR3, ODR3,
STR3, or TWR0 to TWR15
LPC2E
No address (LADR2) matches for IDR2, ODR2, or
STR2
LPC1E
No address (LADR1) matches for IDR1, ODR1, or
STR1