DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 611

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(master output)
(master output)
(slave output)
User processing
ICDRF
ICDRR
SCL
SDA
SDA
IRTR
IRIC
(master output)
(master output)
(slave output)
User processing
Master transmit mode
ICDRR
ICDRF
SCL
SDA
SDA
IRTR
IRIC
Figure 18.11 Example of Operation Timing in Master Receive Mode
Figure 18.12 Example of Stop Condition Issuance Operation Timing
Bit 1
Data 1
Data 2
7
[4] IRIC clear
Bit 0
A
9
8
[1] TRS=0 clear
[6] Set ACKB = 1
A
9
[3]
SCL is fixed low until ICDR is read
in Master Receive Mode (MLS = WAIT = 0)
SCL is fixed low until ICDR is read
Master receive mode
[1] IRIC clear
Bit 7
1
[7] ICDR read
(Data 2)
Bit 7
Bit 6
1
2
(MLS = WAIT = 0)
Bit 6
Bit 5
2
3
[2] ICDR read
Data 1
Undefined value
(Dummy read)
Bit 5
Bit 4
3
Data 2
Data 3
4
Bit 4
Bit 3
4
5
Bit 3
Bit 2
5
6
Bit 2
Bit 1
6
7
[4] IRIC clear
Rev. 2.00 Sep. 28, 2009 Page 569 of 994
Bit 1
Bit 0
SCL is fixed low until
stop condition is issued
7
[9] IRIC clear
8
Bit 0
[3]
A
8
Section 18 I
9
SCL is fixed low until ICDR is read
[11] Set BBSY=0 and
(Stop condition instruction issuance)
A
[8]
9
SCP=0
[5] ICDR read
(Data 1)
Data 1
2
Stop condition generation
C Bus Interface (IIC)
Bit 7
[10] ICDR read
REJ09B0452-0200
1
Data 2
(Data 3)
Bit 6
2
Data 3