DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 730

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.3.2
The FSICR2 control bits are classified into two functionalities: enabling/disabling the FSI
communications and enabling/disabling the FSI internal interrupts.
Rev. 2.00 Sep. 28, 2009 Page 688 of 994
REJ09B0452-0200
Bit
7
6
5
4
3 to 0 ⎯
Bit Name
TE
RE
FSITEIE
FSIRXIE
FSI Control Register 2 (FSICR2)
Initial
Value
0
0
0
0
All 0
EC
R/W
R/W
R/W
R/W
R/W
R/W
Host Description
⎯
⎯
⎯
⎯
⎯
FSI Transmit Enable
Controls FSI transmission and indicates transmission
status in combination with the LFBUSY bit.
0: FSI transmission wait state
[Clearing condition]
When FSI data transmission is completed.
1: When LFBUSY = 0: Starts transmission.
FSI Reception Enable
Controls FSI reception and indicates reception status
in combination with the LFBUSY bit.
0: FSI reception wait state
[Clearing condition]
When FSI data reception is completed.
1: When LFBUSY = 0: Starts reception.
FSI Transmit End Interrupt Enable
0: Disables the FSITEI interrupt request.
1: Enables the FSITEI interrupt request.
FSI Receive Interrupt Enable
0: Disables the FSIRXI interrupt request.
1: Enables the FSIRXI interrupt request.
Reserved
The initial value should not be modified.
When LFBUSY = 1: FSI transmission is in progress
(automatically set).
When LFBUSY = 1: FSI reception is in progress
(automatically set).