DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 493

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and
data is transferred with LSB-first as the start character, as shown in figure 15.23. Therefore, data
in the start character in the figure is H'3B. When using the direct convention type, write 0 to both
the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity,
which is prescribed by the smart card standard.
For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively
and data is transferred with MSB-first as the start character, as shown in figure 15.24. Therefore,
data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to
both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity,
which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of
this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in
both transmission and reception.
15.7.3
Block transfer mode is different from normal smart card interface mode in the following respects.
• If a parity error is detected during reception, no error signal is output. Since the PER bit in
• During transmission, at least 1 etu is secured as a guard time after the end of the parity bit
• Since the same data is not re-transmitted during transmission, the TEND flag in SSR is set
• Although the ERS flag in block transfer mode displays the error signal status as in normal
SSR is set by error detection, clear the bit before receiving the parity bit of the next frame.
before the start of the next frame.
11.5 etu after transmission start.
smart card interface mode, the flag is always read as 0 because no error signal is transferred.
Block Transfer Mode
(Z)
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)
Ds
A
D7
Z
D6
Z
D5
A
D4
A
D3
A
D2
A
D1
A
D0
A
Rev. 2.00 Sep. 28, 2009 Page 451 of 994
Dp
Z
(Z) state
REJ09B0452-0200