DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 674

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Host select register
Note:
20.3.6
LADR2 sets the LPC channel 2 host address. The LADR2 contents must not be changed while
channel 2 is operating (while LPC2E is set to 1).
• LADR2H
Rev. 2.00 Sep. 28, 2009 Page 632 of 994
REJ09B0452-0200
Bits 5 to 3
Bits 15 to 3 in LADR1
Bits 15 to 3 in LADR1
Bits 15 to 3 in LADR1
Bits 15 to 3 in LADR1
Bit
7
6
5
4
3
2
1
0
Bit Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
* When channel 1 is used, the content of LADR1 must be set so that the addresses for
LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)
channels 2, 3, 4, and SCIF are different.
Initial
Value
0
0
0
0
0
0
0
0
I/O Address
Bit 2
0
1
0
1
Slave Host Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 1 and 0
Bits 1 and 0 in LADR1
Bits 1 and 0 in LADR1
Bits 1 and 0 in LADR1
Bits 1 and 0 in LADR1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Channel 2 Address Bits 15 to 8
Set the LPC channel 2 host address.
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
Host Select Register
IDR1 write (data)
IDR1 write (command)
ODR1 read
STR1 read