DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 585

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.3.5
ICCR controls the I
Bit
7
6
5
4
Bit Name
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
C bus interface and performs interrupt flag confirmation.
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
0: I
1: I
I
0: Disables interrupts from the I
1: Enables interrupts from the I
Master/Slave Select
Transmit/Receive Select
MST TRS
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
bus format. In slave receive mode with I
the R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit
mode automatically by hardware.
Modification of the TRS bit during transfer is deferred
until transfer is completed, and the changeover is made
after completion of the transfer (at the rising edge of
the 9th clock).
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
0
0
1
1
2
interface module internal state is initialized. SAR
and SARX can be accessed.
2
operation, and the ports function as the SCL and
SDA input/output pins. ICMR and ICDR can be
accessed.
CPU
CPU.
C bus interface modules are stopped and I
C bus interface modules can perform transfer
0:
1:
0:
1:
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
Rev. 2.00 Sep. 28, 2009 Page 543 of 994
Section 18 I
2
2
C bus interface to the
C bus interface to the
2
C Bus Interface (IIC)
REJ09B0452-0200
2
C bus format,
2
C bus
2
C

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