DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 375

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.1
TDPCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to
CKS0 in TDPCR1. When CKS2 to CKS0 are set to B'111, the external clock is selected. Rising or
falling edge is selected by CKSEG in TDPCSR.
When TDPCNT overflows (H'FFFF changes to H'0000), the OVF flag in TDPCSR is set to 1. In
timer mode, TDPCNT is initialized to H'0000 when the CST bit in TDPCR1 is cleared. In cycle
measurement mode, TDPCNT is cleared when the first edge (the edge selected by the IEDG bit in
TDPCR1) of the measurement period (equal to one input waveform period) is detected.
In timer mode, TDPCNT is always writable. In cycle measurement mode, TDPCNT cannot be
modified. TDPCNT must always be accessed in 16-bit units and cannot be accessed in 8-bit units.
TDPCNT is initialized to H'0000.
12.3.2
TDPWDMX is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is cleared
(timer mode), TDPWDMX is available as a compare match register. When the TDPMDS bit in
TDPCR1 is set to 1 (cycle measurement mode), TDPWDMX is available as a pulse width upper
limit register.
In timer mode, the TDPWDMX value is continually compared with the TDPCNT value. If the
values match, the CMF flag in TDPCSR is set to 1. Note, however, that comparison is disabled in
the second half of a write cycle to TDPWDMX.
In cycle measurement mode, TDPWDMX can be used to set the upper limit value of the
measurement pulse width. When the second edge (the second edge of this period) of the
measurement period is detected, the TDPCNT value is transferred to TDPICR and the values of
TDPICR and TDPWDMX are compared. If the TDPICR value is greater than the TDPWDMX
value, the TWDMXOVF flag in TDPCSR is set to 1. TDPWDMX must always be accessed in 16-
bit units and cannot be accessed in 8-bit units. TDPWDMX is initialized to H'FFFF.
TDP Timer Counter (TDPCNT)
TDP Pulse Width Upper Limit Register (TDPWDMX)
Rev. 2.00 Sep. 28, 2009 Page 333 of 994
REJ09B0452-0200