DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 597

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3.7
ICRES controls IIC internal latch clearance.
Note:
Bit
7 to 5
4
3
2
1
0
* This bit is always read as 1.
Bit Name
—
—
CLR3
CLR2
CLR1
CLR0
I
2
C Bus Control Initialization Register (ICRES)
Initial
Value
All 0
0
1
1
1
1
R/W
R
W*
W*
W*
W*
R/W
Description
Reserved
The initial value should not be changed.
Reserved
IIC Clear 3 to 0
Controls initialization of the internal state of IIC_0 and
IIC_1. (ICRES_0)
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
Controls initialization of the internal state of IIC_2.
(ICRES_2)
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_2 internal latch cleared
0110: Setting prohibited
0111: IIC_2 internal latch cleared
1---: Invalid setting
When a write operation is performed on these bits, a
clear signal is generated for the internal latch circuit of
the corresponding module, and the internal state of the
IIC module is initialized.
These bits can only be written to; they are always read
as 1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do
not use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be
written to in accordance with the setting.
Rev. 2.00 Sep. 28, 2009 Page 555 of 994
Section 18 I
2
C Bus Interface (IIC)
REJ09B0452-0200