DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 624

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 I
18.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 18.9 shows the timing of SCL and SDA outputs in synchronization with the internal
Table 18.9 I
Note:
Rev. 2.00 Sep. 28, 2009 Page 582 of 994
REJ09B0452-0200
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly.
conditions when accessing ICDR.
⎯ Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
⎯ Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
ICDRS)
ICDRR)
* 6t
Usage Notes
2
C Bus Interface (IIC)
cyc
2
C Bus Timing (SCL and SDA Outputs)
when IICX is 0, 12t
cyc
when 1.
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
12t
3t
SCLO
SCLLO
SCLL
cyc
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
*)
– (6t
to 256t
– 3t
– 1t
– 1t
+ 2t
cyc
cyc
cyc
cyc
cyc
or
cyc
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
C bus, neither
Notes
See figure
28.24 (for
reference)