DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 669

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
4
3
2
Bit Name
ABRT
IBFIE3
IBFIE2
Initial
Value
0
0
0
Slave Host Description
R/(W)* ⎯
R/W
R/W
R/W
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register IDR3 and TWR receive
1: [When TWRE = 0 in LADR3]
IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
1: Input data register (IDR2) receive complete
interrupt requests disabled
interrupt requests enabled
Writing 0 after reading ABRT = 1
LPC hardware reset
(LRESET pin falling edge detection)
LPC software reset (LRSTB = 1)
LPC hardware shutdown
(SDWNE = 1 and LPCPD pin falling edge
detection)
LPC software shutdown (SDWNB = 1)
complete interrupt requests disabled
[When TWRE = 1 in LADR3]
Input data register (IDR3) receive complete
interrupt requests enabled
Input data register (IDR3) and TWR receive
complete interrupt requests enabled
Rev. 2.00 Sep. 28, 2009 Page 627 of 994
REJ09B0452-0200

Related parts for DF2117VT20V