DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 387

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(3)
The CMF flag in TDPCSR is set in the last state in which the values in TDPCNT and TDPWDMX
match (timing when TDPCNT updates the matched count value) in timer mode. Accordingly, a
compare match signal is not generated until an additional cycle of the TDPCNT input clock is
generated after a match between the values in TDPCNT and TDPWDMX. For details, see section
12.6.2, Conflict between TDPPDMX Write and Compare Match. Figure 12.6 shows the timing on
which the CMF flag is set.
12.4.2
The TDP operates in cycle measurement mode when the TDPMDS bit in TDPCR1 is set to 1.
(1)
TDPCNT counts up in cycle measurement mode regardless of the setting of the CST bit in
TDPCR1. TDPCNT is cleared to H'0000 when the first edge in the measurement period is
detected, from which state it counts up. Figure 12.7 shows an example of counter operation in
cycle measurement mode.
CMF Setting Timing when a Compare Match Occurs
Counter Operation
φ
TDPCYI
TDPCNT
clear signal
TDPCNT
input clock
TDPCNT
φ
TDPCNT
TDPWDMX
Compare match
signal
CMF
Cycle Measurement Mode
Figure 12.7 Example of Counter Operation in Cycle Measurement Mode
Figure 12.6 Timing of CMF Flag Setting on Compare Match
N
H'0000
N
H'0001
N
H'0002
Rev. 2.00 Sep. 28, 2009 Page 345 of 994
N + 1
H'0003
H'0000
REJ09B0452-0200
H'0001

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