DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 736

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.3.10 FSI Access Host Base Address Registers H and L (FSIHBARH and FSIHBARL)
FSIHBARH and FSIHBARL store the upper 16 bits of the host start address which is necessary to
convert the host address to the SPI flash memory address. The input range of the host address will
be determined based on the host start address set in these registers and the memory size set in
FSISR. If a host address to be input is out of the determined range, Sync will not be returned. If
FW memory cycle is used, bit 31 to bit 28 in FSIHBARH is set as IDSEL. During FSI operation
(in the state where FSIE or FSILIE is set), do not change the setting in this register.
• FSIHBARH
• FSIHBARL
21.3.11 FSI Flash Memory Size Register (FSISR)
FSISR sets the size of SPI flash memory. The host input address range will be determined based
on the size set in this register. Note that the host input address should not be greater than the SPI
flash memory capacity. During FSI operation (in the state where FSIE or FSILIE is set), do not
change the setting in this register.
Rev. 2.00 Sep. 28, 2009 Page 694 of 994
REJ09B0452-0200
Bit
7 to 0 bit 31 to
Bit
7 to 0 bit 23 to
Bit Name
Bit Name
bit 24
bit 16
Initial
Value
All 0
Initial
Value
All 0
EC
R/W
EC
R/W
R/W
R/W
Host Description
⎯
Host Description
⎯
These bits specify bits [31:24] of the host start
address.
These bits specify bits [23:16] of the host start
address.
The settings by bit 19 to bit 16 do not affect the
operation.