DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 605

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 18.7 Sample Flowchart for Operations in Master Transmit Mode
No
No
No
No
No
Write transmit data in ICDR
Write transmit data in ICDR
Read BBSY flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Yes
Set BBSY =1 and
Set BBSY = 0 and
Set MST = 1 and
TRS = 1 in ICCR
SCP = 0 in ICCR
SCP = 0 in ICCR
Transmit mode?
End of transmission?
Initialize IIC
ACKB = 0?
BBSY = 0?
IRIC = 1?
IRIC = 1?
IRIC = 1?
(ACKB = 1?)
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1] Initialization
[2] Test the status of the SCL and SDA lines.
[3] Select master transmit mode.
[4] Start condition issuance
[5] Wait for a start condition generation
[6] Set transmit data for the first byte
[7] Wait for 1 byte to be transmitted.
[8] Test the acknowledge bit
[9] Set transmit data for the second and
[10] Wait for 1 byte to be transmitted.
[11] Determine end of tranfer
[12] Stop condition issuance
(slave address + R/W).
(After writing to ICDR, clear IRIC flag
continuously.)
transferred from the slave device.
subsequent bytes.
continuously.)
(After writing to ICDR, clear IRIC flag
Master receive mode
Rev. 2.00 Sep. 28, 2009 Page 563 of 994
Section 18 I
2
C Bus Interface (IIC)
REJ09B0452-0200

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