DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 285

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3.1
The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only
when TCNT operation is stopped.
[Legend]
x:
Channel Register Name
Channel 2
Common Timer start register
Bit
7
6
5
4
3
2
1
0
Don't care
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
Timer general register A_2
Timer general register B_2
Timer synchro register
Initial
value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source.
See tables 10.4 and 10.5 for details.
Clock Edge 1 and 0
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock cycle
is divided in 2 (φ/4 both edges = φ/2 rising edge). If
phase counting mode is used on channels 1, 2, 4, and
5, this setting is ignored and the phase counting mode
setting has priority. Internal clock edge selection is valid
when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1 and rising edge count is
selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 10.6 to 10.8 for details.
Abbreviation R/W
TGRA_2
TGRB_2
TSTR
TSYR
R/W
R/W
R/W
R/W
Rev. 2.00 Sep. 28, 2009 Page 243 of 994
Initial
Value
H'FFFF H'FE78
H'FFFF H'FE7A 16
H'00
H'00
Address
H'FEB0 8
H'FEB1 8
REJ09B0452-0200
Data Bus
Width
16