DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 858

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4)
The methods for checking of receive data are listed below.
1. Input frequency
2. Division ratio
3. Operating frequency error
4. Bit rate
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation
• Confirmation, H'06, (one byte): Confirmation of a new bit rate
Response
• Response, H'06, (one byte): Response to confirmation of a new bit rate
Rev. 2.00 Sep. 28, 2009 Page 816 of 994
REJ09B0452-0200
The received value of the input frequency is checked to ensure that it is within the range of
minimum to maximum frequencies which matches the clock modes of the specified device.
When the value is out of this range, an input-frequency error is generated.
The received value of the division ratio is checked to ensure that it matches the clock modes of
the specified device. When the value is out of this range, a division ratio error is generated.
Operating frequency is calculated from the received value of the input frequency and the
division ratio. The input frequency is input to the LSI and the LSI is operated at the operating
frequency. The expression is given below.
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register
(SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral
operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that
it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is
calculated using the following expression:
Receive Data Check
Operating frequency = Input frequency ÷ Division ratio
Error (%) = {[
H'06
H'06
(N + 1) × B × 64 × 2
φ × 10
6
(2×n − 1)
] − 1} × 100