DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 533

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.8
(1)
Before starting the CIR reception, set the CIR by following the flow shown in figure 16.7.
The CPHS bit in CCR1 should be set before starting reception. When the CIRI pin is high in the
idle state, set the CPHS bit to 1. When it is low in the idle state, clear the bit to 0. The BRR
register is initialized to H’FF by setting the SRES bit in CCR1 to 1. After setting each register in
the CIR, set the CIRE bit in CCR1 to 1 to enable the CIR reception.
(2)
The CIR is capable of remote-control reception by using the sub clock in watch mode. Before
switching between the system clock and the sub clock, the CIR must be stopped by clearing the
CIRE bit to 0.
CIR Register Setting
Switching between System Clock and Sub Clock
Usage Note
Figure 16.9 CIR Setting Flow
Clear MSTPA3 bit in MSTPCRA to 0.
Set CIRE bit in CCR1 to 1.
Set CPHS bit in CCR1.
Set each register.
Clear CSTR flag.
Start of setting
End of setting
Set CEIR.
Rev. 2.00 Sep. 28, 2009 Page 491 of 994
REJ09B0452-0200