DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 415

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13.3.8
TCONRI controls the input capture function.
13.3.9
TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit
7 to 5
4
3 to 0
Bit
7
6 to 0
Bit Name
ICST
Bit Name
TMRX/Y
Timer Connection Register I (TCONRI)
Timer Connection Register S (TCONRS)
All 0
Initial
Value
All 0
0
All 0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The initial value should not be changed.
Input Capture Start Bit
TMR_X has input capture registers (TICRR and
TICRF). TICRR and TICRF can measure the width of a
pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by
a falling edge is detected on TMRIX after the ICST bit
is set to 1, the contents of TCNT at those points are
captured into TICRR and TICRF, respectively, and the
ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Reserved
The initial values should not be modified.
Description
TMR_X/TMR_Y Access Select
For details, see table 13.4.
0: The TMR_X registers are accessed at addresses
1: The TMR_Y registers are accessed at addresses
Reserved
The initial values should not be modified.
H'(FF)FFF0 to H'(FF)FFF5
H'(FF)FFF0 to H'(FF)FFF5
Rev. 2.00 Sep. 28, 2009 Page 373 of 994
REJ09B0452-0200

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