DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 616

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 I
18.4.6
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 18.16 shows the sample flowchart for the operations in slave transmit mode.
Rev. 2.00 Sep. 28, 2009 Page 574 of 994
REJ09B0452-0200
No
Write transmit data in ICDR
Slave Transmit Operation
No
No
Clear ACKE to 0 in ICCR
2
C Bus Interface (IIC)
Set TRS = 0 in ICCR
Read ACKB in ICSR
Slave transmit mode
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
(ACKB=0 clear)
of transmission
(ACKB = 1)?
Read ICDR
IRIC = 1?
IRIC = 1?
Figure 18.16 Sample Flowchart for Slave Transmit Mode
End
End
Yes
Yes
Yes
[6] Clear IRIC in ICCR
[3], [4] Wait for 1 byte to be transmitted.
[7] Clear acknowledge bit data
[1], [2] If the slave address matches to the address in the first frame
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
[3], [5] Set transmit data for the second and subsequent bytes.
[4] Determine end of transfer.
following the start condition detection and the R/W bit is 1
in slave recieve mode, the mode changes to slave transmit mode.

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