DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 451

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1)
Bit
2
1
0
Bit
7
6
5
Bit Name
MP
CKS1
CKS0
Bit Name
GM
BLK
PE
Initial Value
0
0
0
Initial Value
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
O/E bit settings are invalid in multiprocessor mode.
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 15.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 15.3.9, Bit Rate Register
(BRR)).
Description
GSM Mode
Setting this bit to 1 allows GSM mode operation. In
GSM mode, the TEND set timing is put forward to
11.0 etu* from the start and the clock output control
function is appended. For details, see section
15.7.8, Clock Output Control.
Setting this bit to 1 allows block transfer mode
operation. For details, see section 15.7.3, Block
Transfer Mode.
Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit
is checked in reception. Set this bit to 1 in smart
card interface mode.
Rev. 2.00 Sep. 28, 2009 Page 409 of 994
REJ09B0452-0200