DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 561

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.4
The following shows examples of data transmission/reception for flow control using CTS and
RTS.
(1)
Figure 17.6 shows an example of the initialization flowchart.
(Transmission/reception standby flow)
Initialization
Set data transfer format in FLCR
Set interrupt enable bits in FIER
Clear DLAB bit in FLCR to 0
Set DLAB bit in FLCR to 1
Set RTS bit in FMCR to 1
Data Transmission/Reception with Flow Control
Set FDLH and FDLL
Set FIFO with FFCR
Clear module stop
Start initialization
Set SCIFCR
Figure 17.6 Example of Initialization Flowchart
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Select an input clock with the CKSEL1 and CKSEL0
[2] Set the DLAB bit in FLCR to 1 to enable access to
[3] The initial value of FDLL and FDLH is 0. Set a value
[4] Clear the DLAB bit in FLCR to 0 to disable access to
[5] Select parity with the EPS and PEN bits in FLCR, and
[6] Set the FIFOE bit in FFCR to 1 to enable the FIFO.
[7] Set the EDSSI and ERBFI bits in FIER to 1 to enable a
[8] Set the RTS bit in FMCR to 1.
bits in SCIFCR. Set the SCIF input/output pins with
the SCIFOE1 and SCIFOE0 bits in SCIFCR.
FDLL and FDLH.
within the range from 1 to 65535.
FDLL and FDLH.
set the stop bit with the STOP bit in FLCR. Then, set
the data length with the CLS1 and CLS0 bits in FLCR.
Set the receive FIFO trigger level with the RCVRTRIG1
and RCVRTRIG0 bits in FFCR. Select the best trigger
level to prevent an overflow of the receive FIFO.
modem status interrupt and receive data ready interrupt.
Rev. 2.00 Sep. 28, 2009 Page 519 of 994
REJ09B0452-0200