DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 163

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.2
In interrupt control mode 1, mask control is applied to three levels for interrupt requests other than
NMI and address break by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
• An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
• An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set
to 1, and ICRA to ICRD are set to H'20, H'00, H'00, and H'00, respectively (IRQ2 and IRQ3
interrupts are set to interrupt control level 1, and other interrupts are set to interrupt control level
0) is shown below. Figure 5.8 shows a state transition diagram.
• All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address
• Only NMI, IRQ2, IRQ3, and address break interrupt requests are accepted when I = 1 and UI =
• Only NMI and address break interrupt requests are accepted when I = 1 and UI = 1.
to 0. When the I bit is set to 1, the interrupt request is held pending.
cleared to 0. When both the I and UI bits are set to 1, the interrupt request is held pending.
break > IRQ0 > IRQ1 …)
0.
Exception handling execution
Interrupt Control Mode 1
All interrupt requests
or I
are accepted
Figure 5.8 State Transition in Interrupt Control Mode 1
1, UI
1
I
interrupt requests are accepted
Only NMI and address break
0
I
1, UI
I
0
0
UI
0
Rev. 2.00 Sep. 28, 2009 Page 121 of 994
interrupt control level 1 interrupt
Exception handling
execution or UI
Only NMI, address break, and
requests are accepted
1
REJ09B0452-0200