DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 720

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.6
20.6.1
The LPC interface provides buffering of asynchronous data from the host and slave (this LSI), but
an interface protocol that uses the flags in STR must be followed to avoid data conflict. For
example, if the host and slave both try to access IDR or ODR at the same time, the data will be
corrupted. To prevent simultaneous accesses, IBF and OBF must be used to allow access only to
data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to
TWR15 has been obtained.
Table 20.12 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15.
Rev. 2.00 Sep. 28, 2009 Page 678 of 994
REJ09B0452-0200
Usage Note
Data Conflict