DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 681

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• STR1
Note:
Bit
7
6
5
4
3
2
1
0
Bit Name Initial Value Slave Host Description
DBU17
DBU16
DBU15
DBU14
C/D1
DBU12
IBF1
OBF1
* Only 0 can be written to clear the flag.
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R
R/(W)* R
R/W
R
R
R
R
R
R
R
Command/Data
Defined by User
Defined by User
The user can use these bits as necessary.
When the host writes to IDR1, bit 2 of the I/O
address is written into this bit to indicate whether
IDR1 contains data or a command.
0: Content of input data register (IDR1) is a data
1: Content of input data register (IDR1) is a
The user can use this bit as necessary.
Input Buffer Full
This bit is an internal interrupt source to the slave
(this LSI). The IBF1 flag setting and clearing
conditions are different when the fast Gate A20 is
used. For details, see table 20.5.
0: [Clearing condition]
1: [Setting condition]
When the host writes to IDR1 in I/O write cycle
Output Buffer Full
0: [Clearing conditions]
•
•
1: [Setting condition]
When the slave writes to ODR1
When the slave reads IDR1
command
When the host reads ODR1 in I/O read cycle
When the slave writes 0 to the OBF1 bit
Rev. 2.00 Sep. 28, 2009 Page 639 of 994
REJ09B0452-0200