DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 309
DF2117VT20V
Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VT20HV.pdf
(1040 pages)
Specifications of DF2117VT20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2117VT20V
Manufacturer:
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Quantity:
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Manufacturer:
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10.5
10.5.1
Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of free-
running operation, synchronous counting, and external event counting. Each TGR can be used as
an input capture register or output compare register.
(1)
When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
(a)
Figure 10.6 shows an example of the count operation setting procedure.
Counter Operation
Example of count operation setting procedure
Select output compare register
Select counter clearing source
Operation
Basic Functions
Start count operation
Select counter clock
Operation selection
<Periodic counter>
Periodic counter
Set period
Figure 10.6 Example of Counter Operation Setting Procedure
[1]
[2]
[3]
[4]
[5]
<Free-running counter>
Free-running counter
Start count operation
Rev. 2.00 Sep. 28, 2009 Page 267 of 994
[1]
[2]
[3]
[4]
[5]
Select the counter clock with bits
TPSC2 to TPSC0 inTCR.
At the same time, select the input
clock edge with bits CKEG1 and
CKEG0 in TCR.
For periodic counter operation,
select the TGR to be used as the
TCNT clearing source with bits
CCLR2 to CCLR0 in TCR.
Designate the TGR selected in [2]
as an output compare register by
means of TIOR.
Set the periodic counter cycle in
the TGR selected in [2].
Set the CST bit in TSTR to 1 to
start the counter operation.
REJ09B0452-0200
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