DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 381

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
4
3
2
1
0
Bit Name
IEDG
TDPMDS
CKS2
CKS1
CKS0
Initial
Value R/W
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Input Edge Select
In timer mode, in combination with the value of the POCTL
bit, selects the falling or rising edge of the TDPCYI input for
capturing input.
In cycle measurement mode, this bit does not affect
operation.
When POCTL = 0
0: The falling edge of TDPCYI input is selected
1: The rising edge of TDPCYI input is selected
When POCTL = 1
0: The rising edge of TDPCYI input is selected
1: The falling edge of TDPCYI input is selected
TDP Mode Select
Selects the TDP operating mode.
0: Timer mode
1: Cycle measurement mode
Clock Select 2, 1, 0
These bits select the clock signal for input to TDPCNT. Do
000: Counts the φ internal clock
001: Counts the φ/2 internal clock
010: Counts the φ/4 internal clock
011: Counts the φ/8 internal clock
100: Counts the φ/16 internal clock
101: Counts the φ/32 internal clock
110: Counts the φ/64 internal clock
111: Counts the external clock
(Select the external clock edge with CKSEG in TDPCSR.)
Note: Change this bit when CST = 0 and TDPMDS = 0.
not select the external clock in level control measurement
mode.
In timer mode, the operating mode is input capture and
compare match.
Setting this bit to 1 starts counting by TDPCNT. Clear the
CST bit in TDPCR1 to initialize TDPCNT to H'0000
before setting cycle measurement mode.
Rev. 2.00 Sep. 28, 2009 Page 339 of 994
REJ09B0452-0200

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