DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 600

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 I
Rev. 2.00 Sep. 28, 2009 Page 558 of 994
REJ09B0452-0200
Bit
4
Bit Name
ICDRE
2
C Bus Interface (IIC)
Initial
Value
0
R/W
R
0: Indicates that the data has been already written to
1: Indicates that data has been transferred from ICDRT
Description
Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
[Setting conditions]
•
•
[Clearing conditions]
•
•
•
•
Note that if the ACKE bit is set to 1 with I
thus enabling acknowledge bit decision, ICDRE is not
set when data transmission is completed while the
acknowledge bit is 1.
When ICDRE is set due to the condition (2) above,
ICDRE is temporarily cleared to 0 when data is written
to ICDR (ICDRT); however, since data is transferred
from ICDRT to ICDRS immediately, ICDRE is set to 1
again. Do not write data to ICDR when TRS = 0
because the ICDRE flag value is invalid during the
time.
ICDR (ICDRT) or ICDR is initialized.
to ICDRS and is being transmitted, or the start
condition has been detected or transmission has
been complete, thus allowing the next data to be
written to.
When the start condition is detected from the bus
line state with I
When data is transferred from ICDRT to ICDRS.
1. When data transmission completed while
2. When data is written to ICDR in transmit mode
When data is written to ICDR (ICDRT).
When the stop condition is detected with I
format or serial format.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3
to CLR0 bits in DDCSWR.
ICDRE = 0 (at the rise of the 9th clock pulse).
after data transmission was completed while
ICDRE = 1.
2
C bus format or serial format.
2
C bus format
2
C bus