DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 498

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.7.7
Data reception in smart card interface mode is identical to that in normal serial communication
interface mode. Figure 15.29 shows the data re-transfer operation during reception.
1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI
2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1.
3. If no parity error is detected, the PER bit in SSR is not set to 1. In this case, data is determined
Figure 15.30 shows a sample flowchart for reception. In reception, setting the RIE bit to 1 allows
an RXI interrupt request to be generated when the RDRF flag is set to 1. If an error occurs during
reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI)
request is generated and the error flag must be cleared. Even if a parity error occurs and PER is set
to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read.
Note: For operations in block transfer mode, see section 15.4, Operation in Asynchronous Mode.
Rev. 2.00 Sep. 28, 2009 Page 456 of 994
REJ09B0452-0200
interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the
next parity bit is sampled.
to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt
request is generated if the RIE bit in SCR is set.
RDRF
PER
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp
Serial Data Reception (Except in Block Transfer Mode)
Figure 15.29 Data Re-transfer Operation in SCI Reception Mode
n th transfer frame
[2]
[1]
DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransfer frame
[3]
[3]
(DE)
Ds D0 D1 D2 D3 D4
transfer frame
(n + 1) th