DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 826

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3. FKEY is cleared to H'00 for protection.
4. The download result must be confirmed by the value of the DPFR parameter. Check the value
5. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The
6. Initialization is executed. The initialization program is downloaded together with the
Rev. 2.00 Sep. 28, 2009 Page 784 of 994
REJ09B0452-0200
⎯ To hold a level-detection interrupt request, the interrupt must continue to be input until the
⎯ Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the
of the DPFR parameter (one byte of start address of the download destination specified by
FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally.
If the value is not H'00, the source that caused download to fail can be investigated by the
description below.
⎯ If the value of the DPFR parameter is the same as that before downloading, the setting of
⎯ If the value of the DPFR parameter is different from that before downloading, check the SS
settable operating frequency of the FPEFEQ parameter ranges from 8 to 32 MHz. When the
frequency is set otherwise, an error is returned to the FPFR parameter of the initialization
program and initialization is not performed. For details on setting the frequency, see section
24.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of
CPU).
programming program to the on-chip RAM. The entry point of the initialization program is at
the address which is 32 bytes after #DLTOP (start address of the download destination
specified by FTDAR). Call the subroutine to execute initialization by using the following
steps.
MOV.L #DLTOP+32,ER2
JSR
NOP
⎯ The general registers other than R0L are held in the initialization program.
⎯ R0L is a return value of the FPFR parameter.
⎯ Since the stack area is used in the initialization program, a stack area of 128 bytes at the
⎯ Interrupts can be accepted during execution of the initialization program. Make sure the
download is completed.
SCO bit to 1.
the start address of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit in FTDAR.
bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY
setting, respectively.
maximum must be allocated in RAM.
program storage area and stack area in the on-chip RAM and register values are not
overwritten.
@ER2
; Set entry address to ER2
; Call initialization routine