DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 777

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. First, select the clock used in A/D conversion.
When changing the operating mode or analog input channel, to prevent incorrect operation, first
clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set at the same
time the operating mode or analog input channel is changed.
22.4.1
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1 by
2. When A/D conversion is completed, the result is transferred to the A/D data register
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit
software, the TMR, or the TPU.
corresponding to the channel.
1 at this time, an ADI interrupt request is generated.
is automatically cleared to 0 and the A/D converter enters wait state. When the ADST bit is
cleared to 0 during A/D conversion, the conversion stops and the A/D converter enters wait
state.
Operation
Single Mode
Rev. 2.00 Sep. 28, 2009 Page 735 of 994
REJ09B0452-0200

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