DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 161

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 5.9 shows operations and control signal functions in each interrupt control mode.
Table 5.9
[Legend]
Ο:
IM:
PR:
—:
5.6.1
In interrupt control mode 0, interrupt requests other than NMI and address break are masked by
ICR and the I bit of CCR in the CPU. Figure 5.7 shows a flowchart of the interrupt acceptance
operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
3. If the I bit in CCR is set to 1, the interrupt controller holds pending interrupt requests other
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
Interrupt
Control Mode INTM1
0
1
interrupt request is sent to the interrupt controller.
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
than NMI and address break. If the I bit is cleared to 0, any interrupt request is accepted.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
interrupts.
Interrupt operation control is performed
Used as an interrupt mask bit
Priority is set
Not used
Interrupt Control Mode 0
Operations and Control Signal Functions in Each Interrupt Control Mode
0
Setting
INTM0
0
1
Ο
Ο
I
IM
IM
Interrupt Acceptance
3-Level Control
UI
—
IM
Control
Rev. 2.00 Sep. 28, 2009 Page 119 of 994
ICR
PR
PR
Default Priority
Determination
Ο
Ο
REJ09B0452-0200